1. Technical Field
Embodiments of the present invention relate to turbo decoders and, more particularly, relate to memory techniques for a turbo decoder.
2. Description of the Related Art
Telecommunications involves sending information from a transmitter to a receiver. Channel coding is a process performed by the transmitter of adding extra information bits or redundant bits to the information to be sent. The receiver then uses the redundant bits to help it identify the sent message.
Typically signals are encoded before being sent to a cellular telephone using a method of encoding defined in a cellular standards specification. An encoder in the transmitter adds redundancy using a predetermined method and a decoder in the receiver uses knowledge of the redundancy method to increase reliability of data demodulation and decoding. Typically high latency sensitive traffic signals such as voice are encoded using a convolutional coder and lower latency traffic signals such as data are encoded using a turbo encoder. While cellular standards specifications specify the requirement for turbo encoding a signal, these cellular standards specifications do not typically specify the operations for turbo decoding a signal. Turbo decoding is basically defined as the reverse process of turbo encoding.
Turbo encoding is one method of encoding by adding redundancy. A turbo encoder uses an interleaver to shuffle the bits to be transmitted into a random order. The interleaving process increases the probability that errors introduced while the coded data is transmitted can be overcome and the original information reconstructed at the receiver. A turbo decoder is responsible for reversing the interleaving process. To unwind the interleaving procedure, it saves power to generate the desired bit's address in memory rather than move the data itself. The turbo decoder uses an iterative algorithm. The Turbo Decoder decodes using plural maximum a posteriori (MAP) estimates. The turbo decoder alternates between processing received samples relating to (xk, zk) called even MAP estimates, and processing received samples relating to z′k called odd MAP estimates. The two MAP estimates are together called an iteration. For example, if the turbo decoder performs four iterations that means it would have processed 8 MAP estimates.
The turbo encoder and turbo decoder are an integral part of telecom standards with data rates reaching upwards of 100 Mbps (million bits per second). These high data rates create new demands on processing speed which require multiple bits to be processed in parallel. To achieve this, a parallel architecture of multiple turbo decoder engines is used. To further increase throughput, the input can be double buffered. In this architecture, one input buffer is loaded while the other is decoded. In this case, the interleaver addresses must be generated twice during a turbo decode operation; once during the load phase and once during the decode phase. There are two ways to turbo decode in parallel. A first way is to break a coded block into smaller sub-blocks, and process those in parallel. A second way is to process multiple coded blocks in parallel. The first approach increases decoding latency and input random access memory (RAM) requirements. The second approach may have problems with collisions.
The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
The details of the preferred embodiments will be more readily understood from the following detailed description when read in conjunction with the accompanying drawings wherein: